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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com st16c2552 2.97v to 5.5v dual uart with 16-byte fifo october 2006 rev. 4.2.1 general description the st16c2552 (2552) is a dual universal asynchronous receiver and transmitter (uart). the st16c2552 is an improved version of the pc16552 uart. the 2552 provides enhanced uart functions with 16 byte fifos, a modem control interface, and data rates up to 4 mbps. onboard status registers provide the user with error indications and operational status. system interrupts and modem control features may be tailored by external software to meet specific user requirements. indepedendent programmable baud rate generators are privded to select transmit and receive clock rates from 50 bps to 4 mbps. the baud rate generator can be configured for either crystal or external clock input. an internal loop-back capability allows onboard diagnostics. the 2552 provides block mode data transfers (dma) through fifo controls. dma transfer monitoring is provided through the signals txrdy# and rxrdy#. an alternate function register provides the user with the ability to initialize both uarts concurrently. the 2552 is available in the 44-plcc package. applications ? portable appliances ? telecommunication network routers ? ethernet network routers ? cellular data devices ? factory automation and process controls features added feature in devices with top marking "a2 yyww" and newer: 5 volt tolerant inputs ? pin-to-pin and functionally compatible to national pc16552 and exar?s xr16l2752 and xr16c2852 ? 4 mbps transmit/receive operation (64 mhz external clock frequency) ? 2 independent uart channels register set compatible to 16c550 16 byte transmit fifo to reduce the bandwidth requirement of the external cpu 16 byte receive fifo with error tags to reduce the bandwidth requirement of the external cpu 4 selectable rx fifo trigger levels fixed transmit fifo in terrupt trigger level full modem interface (cts#, rts#, dsr#, dtr#, ri#, cd#) ? dma operation and dma monitoring via txrdy# and rxrdy# pins ? uart internal register sections a & b may be written to concurrently ? multi-function output allows more package functions with few i/o pins ? programmable character lengths (5, 6, 7, 8) with even, odd, or no parity ? crystal oscillator or external clock input f igure 1. st16c2552 b lock d iagram mfa# (op2a#, baudouta#, or rxrdya#) mfb# (op2b#, baudoutb#, or rxrdyb#) xtal1 xtal2 crystal osc/buffer txa (or txira) 8-bit data bus interface uart channel a 16 byte tx fifo 16 byte rx fifo brg tx & rx uart regs 3.3v or 5v vcc gnd 2552blk uart channel b (same as channel a) a2:a0 d7:d0 cs# chsel inta intb iow# ior# reset txrdya# txrdyb# cts#a/b, ri#a/b, cd#a/b, dsr#a/b rxa (or rxira) modem control logic dtr#a/b, rts#a/b txb (or txirb) rxb (or rxirb)
st16c2552 2 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus st16c2552cj44 44-lead plcc 0c to +70c active st16c2552ij44 44-lead plcc -40c to +85c active 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 a0 xtal1 gnd xtal2 a1 a2 chsel intb rxa txa dtra# rtsa# mfa# inta vcc txrdyb# rib# cdb# dsrb# cs# mfb# iow# reset gnd rtsb# ior# rxb txb dtrb# ctsb# d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# st16c2552 44-pin plcc
st16c2552 3 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo pin descriptions pin description n ame 44-plcc p in # t ype d escription data bus interface a2 a1 a0 15 14 10 i address data lines [2:0]. these 3 address li nes select one of the internal registers in uart channel a/b during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 9 8 7 6 5 4 3 2 i/o data bus lines [7:0] (bidirectional). ior# 24 i input/output read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an inte rnal register pointed to by the address lines [a2:a0]. the data byte is placed on the data bus to allow the host processor to read it on the rising edge. iow# 20 i input/output write strobe (active low). the falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal regis - ter pointed by the address lines. cs# 18 i uart chip select (active low). this func tion selects channel a or b in accordance with the logical state of the chsel pin. this allows data to be transferred between the user cpu and the 2552. chsel 16 i channel select - uart channel a or b is selected by the logical state of this pin when the cs# pin is a logic 0. a logic 0 on the chsel selects the uart channel b while a logic 1 selects uart channel a. normally, chsel could just be an address line from the user cpu such as a3. bit-0 of the alternate function register (afr) can tempo - rarily override chsel function, allowing the user to write to both channel register simultaneously with one write cycle when cs# is low. it is especially useful during the initialization routine. inta 34 o uart channel a interrupt output (active high). a logic high indicates channel a is requesting for service. for more details, see figures 16 - 21 . intb 17 o uart channel b interrupt output (active high). a logic high indicates channel b is requesting for service. for more details, see figures 16 - 21 . txrdya# 1 o uart channel a transmitter ready (active low). the output provides the tx fifo/thr status for transmit channel a. if it is not used, leave it unconnected. txrdyb# 32 o uart channel b transmitter ready (active low). the output provides the tx fifo/ thr status for transmit channel b. if it is not used, leave it unconnected. modem or serial i/o interface
st16c2552 4 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 mfa# 35 o multi-function output channel a. this ou tput pin can function as the op2a#, baud - outa#, or rxrdya# pin. one of these ou tput signal functions can be selected by the user programmable bits 1-2 of the alternate function register (afr). these sig - nal functions are described as follows: 1) op2a# - when op2a# (active low) is sele cted, the mf# pin is a logic 0 when mcr bit-3 is set to a logic 1 (see mcr bit-3). m cr bit-3 defaults to a logic 1 condition after a reset or power-up. 2) baudouta# - when baudouta# function is selected, the 16x baud rate clock output is available at this pin. 3) rxrdya# - rxrdya# (active low) is int ended for monitoring dma data transfers. see ta b l e 2 for more details. if it is not used, leave it unconnected. mfb# 19 o multi-function output channelb. this ou tput pin can function as the op2b#, baud - outb#, or rxrdyb# pin. one of these outp ut signal functions can be selected by the user programmable bits 1-2 of the alternate function register (afr). these sig - nal functions are described as follows: 1) op2b# - when op2b# (active low) is sele cted, the mf# pin is a logic 0 when mcr bit-3 is set to a logic 1 (see mcr bit-3). m cr bit-3 defaults to a logic 1 condition after a reset or power-up. 2) baudoutb# - when baudoutb# function is selected, the 16x baud rate clock output is available at this pin. 3) rxrdyb# - rxrdyb# (active low) is intended for monitoring dma data transfers. see ta b l e 2 for more details. if it is not used, leave it unconnected. txa 38 o uart channel a transmit data. if it is not used, leave it unconnected. rxa 39 i uart channel a receive data. normal receive data input must idle at logic 1 condi - tion. if it is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsa# 36 o uart channel a request-to-send (active low) or general purpose output. if it is not used, leave it unconnected. ctsa# 40 i uart channel a clear-to-send (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. dtra# 37 o uart channel a data-terminal-ready (active lo w) or general purpos e output. if it is not used, leave it unconnected. dsra# 41 i uart channel a data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cda# 42 i uart channel a carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. pin description n ame 44-plcc p in # t ype d escription
st16c2552 5 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo pin type: i=input, o=output, i/o= input/output, od=output open drain. ria# 43 i uart channel a ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. txb 26 o uart channel b transmit data. if it is not used, leave it unconnected. rxb 25 i uart channel b receive data. normal receive data input must idle at logic 1 condi - tion. if it is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsb# 23 o uart channel b request-to-send (active low) or general purpose out put. if it is not used, leave it unconnected. ctsb# 28 i uart channel b clear-to-send (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. dtrb# 27 o uart channel b data-terminal-ready (active lo w) or general purpos e output. if it is not used, leave it unconnected. dsrb# 29 i uart channel b data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cdb# 30 i uart channel b carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. rib# 31 i uart channel b ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ancillary signals xtal1 11 i crystal or external clock input. xtal2 13 o crystal or buffered clock output. reset 21 i reset (active high) - a longer than 40 ns logic 1 pulse on this pin will reset the internal registers and all outputs. the uart transmi tter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see external reset conditions). vcc 44, 33 pwr 3.3v to 5v power supply. all inputs are 5v tolerant for devices with top marking of "a2 yyww" and newer. gnd 22, 12 pwr power supply common, ground. pin description n ame 44-plcc p in # t ype d escription
st16c2552 6 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 1.0 product description the 2552 provides serial asynchronous receive data syn chronization, parallel-to-ser ial and serial-to-parallel data conversions for both the transmitter and receiver sections. these functions ar e necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integrity is ensure d by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especia lly when manufactured on a single integrated silicon chip. the 2552 represents such an integration with greatly enhanced features. the 2552 is fabr icated with an advanced cmos process. the 2552 is an upward solution that provides a dual uart capability with 16 bytes of transmit and receive fifo memory, instead of none in t he 16c2450. the 2552 is designed to work with high speed modems and shared network environments, that require fast data proc essing time. increased performance is realized in the 2552 by the transmit and receive fifo?s. this allows the external processor to handle more networking tasks within a given time. for example, the st16c2450 without a receive fifo, w ill require unloading of the rhr in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbps). this means the external cpu will have to service the rece ive fifo less than every 10 0 microseconds. however with the 16 byte fifo in t he 2552, the data buffer will not require unloading/loa ding for 1.53 ms. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. in addition, the 4 selectab le receive fifo trigger inte rrupt levels is uniquely provided for maximum data throughput performanc e especially when operating in a multi-channel environment. the fifo memo ry greatly reduces the band width requirement of the external controlling cpu, increases performance, and reduces power consumption. the 2552 is capable of operation up to 4 mbps with a 64 mhz clock. with a crystal or external clock input of 14.7456 mhz the user can select data rates up to 921.6 kbps. the rich feature set of the 2552 is available through internal registers. selectable receive fifo trigger levels, selectable tx and rx baud rates, and modem interface controls are all standard features. following a power on reset or an external reset, the 2552 is software compatible with the 16l2752 and 16c2852.
st16c2552 7 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the 2552 data interface supports the in tel compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is requir ed to operate a data bus transaction. each bus cycle is asynchronous using cs#, ior# and iow# signals. both uart channels share the same data bus for host operations. t he data bus interconnections are shown in figure 3 . . 2.2 device reset the reset input resets the internal registers and the seri al interface outputs in both channels to their default state (see the ta b l e 11 ). an active high pulse of lo nger than 40 ns duration will be required to activate the reset function in the device. 2.3 channel a and b selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. a logic 0 on chip select pin (cs#) allows the user to select the uart and then using the channel select (chsel) pin, the user can select channel a or b to configure, send transmit data and/or unload receive data to/from th e uart. individual channel select functions are shown in table 1 . f igure 3. st16c2552 d ata b us i nterconnections t able 1: c hannel a and b s elect cs# chsel f unction 1 x uart de-selected 0 1 channel a selected 0 0 channel b selected vcc vcc (op2a#) dsra# ctsa# rtsa# dtra# rxa txa ria# cda# (op2b#) dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_cs# uart_chsel ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 cs# chsel d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta (rxrdya#) txrdya# (rxrdya#) txrdya# (rxrdyb#) txrdyb# (rxrdyb#) txrdyb# uart_reset reset serial interface of rs-232, rs-485 serial interface of rs-232, rs-485 2750int (baudoutb#) (baudouta#) pins in parentheses become available through the mf# pin. mf# a/b becomes rxrdy# a/b when afr[2:1] = '10'. mf# a/b becomes op2 # a/b when afr[2:1] = '00'. mf# a/b becomes baudout# a/b when afr[1:0] = '01'.
st16c2552 8 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 2.4 channel a and b internal registers each uart channel in the 2552 has a set of enhanced registers for cont rolling, monitoring and data loading and unloading. the configuration register set is compat ible to those already available in the standard single 16c550 and dual st16c2550. these r egisters function as data holding regi sters (thr/rhr), interrupt status and control registers (isr/ier), a fi fo control register (fcr), receive lin e status and control registers (lsr/ lcr), modem status and control regist ers (msr/mcr), programmable data rate (clock) divisor registers (dll/ dlm), and a user accessible scratchpad register (spr). beyond the general 16c 2550 features and capabilities, the 2552 offers th e alternate function register which allows simultaneous writes to both channels. all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 15 . 2.5 simultaneous write to channel a and b during a write mode cycle, the setting of alternate function register (afr ) bit-0 to a logic 1 will override the chsel selection and allows a simultan eous write to both uart channel se ctions. this functional capability allow the registers in both uart channels to be modified concurrently, saving indivi dual channel initialization time. caution should be exer cised, however, when using this capability. any in-process se rial data transfer may be disrupted by changing an active channel?s mode. 2.6 dma mode the device does not support direct memory access. th e dma mode (a legacy term) in this document doesn?t mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a/b (mf# a/b becomes rxrdy# a/b output when afr[2:1] = ?10?) and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional fl exibility to the user for block mode operation. the lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the 2552 is placed in single-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit- 3 = 1), the user takes advantage of block mode opera tion by loading or unloading the fifo in a block sequence determined by the programmed trigger level. the following table show their behavior. also see figures 16 through 21 . t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy# a/b 0 = 1 byte. 1 = no data. 0 = at least 1 byte in fifo 1 = fifo empty. 1 to 0 transition when fifo reaches the trigger level, or timeout occurs. 0 to 1 transition when fifo empties. txrdy# a/b 0 = thr empty. 1 = byte in thr. 0 = fifo empty. 1 = at least 1 byte in fifo. 0 = fifo has at least 1 empty location. 1 = fifo is full.
st16c2552 9 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo 2.7 inta and intb ouputs the inta and intb interrupt outputs change according to the operating mode and enahnced features setup. ta b l e s 3 and 4 summarize the operating behavior for the tr ansmitter and receiver. also see figures 16 through 21 . 2.8 crystal oscillator or ext. clock input the 2552 includes an on-chip oscillator (xtal1 and xt al2) to produce a clock for both uart sections in the device. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. see?programmable baud rate generator? on page 10. f igure 4. t ypical oscillator connections the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 2 ), with an external 500k ? to 1 m ? resistor across it. alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generato r for standard or custom rates. typica l oscillator connections are shown in figure 4 . for further reading on oscilla tor circuit please see application note dan108 on exar?s web site. t able 3: inta and intb p ins o peration for t ransmitter fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin 0 = a byte in thr 1 = thr empty 0 = at least 1 byte in fifo 1 = fifo empty t able 4: inta and intb p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin 0 = no data 1 = 1 byte 0 = fifo below trigger level 1 = fifo above trigger level c1 22-47 pf c2 22-47 pf y1 1.8432 mhz to 24 mhz r1 0-120 ? (optional) r2 500 ? ? 1 ? xtal1 xtal2
st16c2552 10 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 2.9 programmable baud rate generator a single baud rate generator is provided for the trans mitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator is capa ble of operating with a crystal frequency of up to 24 mhz. however, with an external clock input on xtal 1 pin and a 2k ohms pull-up resistor on xtal2 pin (as shown in figure 5 ) it can extend its operation up to 64 mhz (4mbps serial data rate) at room temperature and 5.0v. f igure 5. e xternal c lock c onnection for e xtended d ata r ate to obtain maximum data rate, it is necessary to use full rail swing on the clock input. see external clock operating frequency over power supply voltage chart in figure 6 . f igure 6. o perating f requency c hart . r equires a 2k ohms pull - up resistor on xtal2 pin to increase operating speed . the 2552 divides the basic external cl ock by 16. the basic 16x clock provi des table rates to support standard and custom applications using the sa me system design. the baud rate ge nerator divides this 16x clock by any divisor from 1 to 2 16 -1. the rate table is configured via th e dll and dlm internal register functions. customized baud rates can be achieved by selecting th e proper divisor values for the msb and lsb sections of baud rate generator. 2k xtal1 xtal2 r1 vcc external clock vcc gnd 60 50 40 30 3.0 4.5 5.5 3.5 4.0 5.0 suppy voltage xtal1 external clock frequency in mhz. 70 80 85 o c 25 o c -40 o c operating frequency for st16c2550 with external clock and a 2k ohms pull-up resistor on xtal2 pin.
st16c2552 11 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo table 5 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x sampling rate. when using a non-standard frequency crystal or ex ternal clock, the divisor value can be calculated for dll/dlm with the following equation. 2.10 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter se nds the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop -bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.10.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.10.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. divisor (decimal) = (xtal1 or external clock frequency ) / (serial data rate x 16) t able 5: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 400 2304 900 09 00 0 2400 384 180 01 80 0 4800 192 c0 00 c0 0 9600 96 60 00 60 0 19.2k 48 30 00 30 0 38.4k 24 18 00 18 0 76.8k 12 0c 00 0c 0 153.6k 6 06 00 06 0 230.4k 4 04 00 04 0 460.8k 2 02 00 02 0 921.6k 1 01 00 01 0
st16c2552 12 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 2.10.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 16 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when the fifo and the tsr become empty. 2.11 receiver the receiver section contains an 8-bit receive shift register (rsr) and 16 bytes of fifo which includes a byte-wide receive holding regi ster (rhr). the rsr uses the 16x for ti ming. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter star ts counting at the 16x. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluati ng the start bit in this manner prevents the receiver from assembling a false ch aracter. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are f igure 7. t ransmitter o peration in non -fifo m ode f igure 8. t ransmitter o peration in fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock transmit data shift register (tsr) data byte thr interrupt (isr bit-1) when tx fifo becomes empty. fifo is enabled by fcr bit-0=1. transmit fifo 16x clock txfifo1 thr
st16c2552 13 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiv ing a character or delay until it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits ti me. this is equivalent to 3.7- 4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.11.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 16 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 9. r eceiver o peration in non -fifo m ode f igure 10. r eceiver o peration in fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2 receive data shift register (rsr) rxfi 16x clock error tags (16-sets) error tags in lsr bits 4:2 16 bytes by 11-bit wide fifo receive data characters data bit validation rx fifo rhr receive data byte and errors rhr interrupt (isr bit-2) when fifo fills up to trigger level. fifo is enabled by fcr bit-0=1
st16c2552 14 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 2.12 internal loopback the 2552 uart provides an intern al loopback capability for system di agnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 11 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ig nored. caution: the rx input must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. f igure 11. i nternal l oop b ack in c hannel a and b txa/txb rxa/rxb modem / general purpose control logic internal data bus lines and control signals rtsa#/rtsb# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) ctsa#/ctsb dtra#/dtrb# dsra#/dsrb# ria#/rib# cda#/cdb# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc (op2a#/op2b#) vcc
st16c2552 15 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo 3.0 uart internal registers each of the uart channel in the 2552 has its own set of configuration registers selected by address lines a0, a1 and a2 with cs# and chsel selecting the channel. the registers are 16c550 compatible. the complete register set is shown in table 6 and table 7 . t able 6: uart channel a and b uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1 0 0 1 dlm - div latch high byte read/write lcr[7] = 1 0 1 0 afr - alternate function register read/write lcr[7] = 1 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr[7] = 0 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratch pad register read/write
st16c2552 16 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 . 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 12. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 11. t able 7: internal registers description. a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0 0 0 0 modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable 0 1 0 isr rd fifos enabled fifos enabled 0 0 int source bit-3 int source bit-2 int source bit-1 int source bit-0 0 1 0 fcr wr rx fifo trigger bit-1 rx fifo trigger bit-0 0 0 dma mode enable tx fifo reset rx fifo reset fifos enable 0 1 1 lcr rd/wr divisor enable set tx break set par - ity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0 0 0 internal loop - back enable op2# output control rsvd (op1#) rts# output control dtr# output control 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram - ing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 1 0 afr rd/wr 0 0 0 0 0 rxrdy# select baudout# select concur - rent write
st16c2552 17 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo 4.3 baud rate generator divisors (dll and dlm) - read/write the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter. the rate is programmed through registers dll and dlm which are on ly accessible when lcr bit-7 is set to ?1?. see?programmable baud rate genera tor? on page 10. for more details. 4.4 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.4.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interr upts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 4.4.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the st16c2552 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates tran smit fifo is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit re ady interrupt which is issued whenever the tx fifo becomes empty. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an in terrupt when the character with errors is read out of the fifo. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt.
st16c2552 18 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[7:4]: reserved 4.5 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with f our interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt le vel to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 8 , shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.5.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty. ? msr is by any of the msr bits 0, 1, 2 and 3. 4.5.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). t able 8: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of i nterrupt l evel b it -3 b it -2 b it -1 b it -0 1 0 1 1 0 lsr (receiver line status register) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 1 0 0 rxrdy (received data ready) 4 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 msr (modem status register) - 0 0 0 1 none (default)
st16c2552 19 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 8 ). isr[5:4]: reserved isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.6 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: reserved fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 9 shows the complete selections. t able 9: t ransmit and r eceive fifo t rigger l evel s election fcr b it -7 fcr b it -6 r eceive t rigger l evel c ompatibility 0 0 1 1 0 1 0 1 1 (default) 4 8 14 table-a. 16c550, 16c2550, 16c2552, 16c554, 16c580 com - patible.
st16c2552 20 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 4.7 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 10 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2
st16c2552 21 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr[5] = logic 0, parity is not forced (default). ? lcr[5] = logic 1 and lcr[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr[5] = logic 1 and lcr[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, logic 0, state). this co ndition remains, until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected. (default) ? logic 1 = divisor latch registers are selected. 4.8 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output to a logic 1 (default). ? logic 1 = force dtr# output to a logic 0. mcr[1]: rts# output the rts# pin is a modem control output. if the modem in terface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# output to a logic 1 (default). ? logic 1 = force rts# output to a logic 0. mcr[2]: op1# output op1# is not available as an output pin on the 2552. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. t able 10: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
st16c2552 22 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 mcr[3]: op2# output op2# is available as an output pin on the 2552 when afr[ 2:1] = ?00?. in the loopback mode, mcr[3] is used to write the state of the modem cd# interface si gnal. also see pin descriptions for mf# pins. ? logic 0 = forces op2# output to a logic 1 (default). ? logic 1 = forces op2# output to a logic 0. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 11 . mcr[7:5]: reserved 4.9 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding regi ster empty indicator. this bit indica tes that the transmitter is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the host when the thr inte rrupt enable is set. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift regist er. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. in th e fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmi t fifo contains at least 1 byte.
st16c2552 23 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in the fifo. 4.10 modem status register (msr) - read only this register provides the current state of the modem interface signals, or othe r peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status normally msr bit-4 bit is the complim ent of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the ct s# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the compliment of the ri# input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used.
st16c2552 24 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 msr[7]: cd input status normally this bit is the compliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.11 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.12 baud rate generator registers (dll and dlm) - read/write the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: ? baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also. 4.13 alternate function register (afr) - read/write this register is used to select spec ific modes of mf# operation and to allow both uart register sets to be written concurrently. afr[0]: concurrent write mode when this bit is set, the cpu can wr ite concurrently to the same register in both uarts. this function is intended to reduce the dual uart initialization time . it can be used by the cpu when both channels are initialized to the same state. the external cpu can set or clear this bit by accessing either register set. when this bit is set, the channe l select pin still selects the channel to be accessed during read operations. the user should ensure that lcr bit-7 of both channels are in t he same state before executing a concurrent write to the registers at address 0, 1, or 2. ? logic 0 = no concurrent write (default). ? logic 1 = register set a and b are written concurrently with a single external cpu i/o write operation. afr[2:1]: mf# output select these bits select a signal function for output on the mf# a/b pins. these signal function are described as: op2#, baudout#, or rxrdy#. only one sign al function can be selected at a time. afr[7:3]: reserved all are initialized to logic 0. b it -2 b it -1 mf# f unction 0 0 op2# (default) 0 1 baudout# 1 0 rxrdy# 1 1 reserved
st16c2552 25 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo t able 11: uart reset conditions for channel a and b registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx afr bits 7-0 = 0x00 rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff i/o signals reset state tx logic 1 mf# logic 1 rts# logic 1 dtr# logic 1 txrdy# logic 0 int logic 0
st16c2552 26 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to vcc+0.3 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (44-plcc) theta-ja = 50 o c/w, theta-jc = 21 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v s ymbol p arameter t op m arking "a2 yyww" and newer u nits l imits 3.3v m in m ax l imits 5.0v m in m ax l imits 3.3v m in m ax l imits 5.0v m in m ax c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc 2.4 5.5 3.0 5.5 v v il input low voltage -0.3 0.8 -0.5 0.8 -0.3 0.8 -0.5 0.8 v v ih input high voltage 2.0 vcc 2.2 vcc 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 0.4 v i ol = 6 ma v ol output low voltage 0.4 0.4 v i ol = 4 ma v oh output high voltage 2.4 2.4 v i oh = -6 ma v oh output high voltage 2.0 2.0 v i oh = -1 ma i il input low leakage current 10 10 10 10 ua i ih input high leakage current 10 10 10 10 ua c in input pin capacitance 5 5 5 5 pf i cc power supply current 1.2 3 1.2 3 ma
st16c2552 27 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97 to 5.5v 70 p f load where applicable s ymbol p arameter l imits 3.3 m in m ax l imits 5.0 m in m ax u nit - crystal frequency 20 24 mhz clk clock pulse duration 17 8 ns osc external clock frequency 30 64 mhz t as address setup time 5 0 ns t ah address hold time 10 5 ns t cs chip select width 66 50 ns t rd ior# strobe width 35 25 ns t dy read cycle delay 40 30 ns t rdv data access time 35 25 ns t dd data disable time 0 25 0 15 ns t wr iow# strobe width 40 25 ns t dy write cycle delay 40 30 ns t ds data setup time 20 15 ns t dh data hold time 5 5 ns t wdo delay from iow# to output 50 40 ns t mod delay to set interrupt from modem input 40 35 ns t rsi delay to reset interrupt from ior# 40 35 ns t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 45 40 ns t si delay from start to interrupt 45 40 ns t int delay from initial int reset to transmit start 8 24 8 24 bclk t wri delay from iow# to reset interrupt 45 40 ns t ssr delay from stop to set rxrdy# 1 1 bclk t rr delay from ior# to reset rxrdy# 45 40 ns t wt delay from iow# to set txrdy# 45 40 ns t srt delay from center of start to reset txrdy# 8 8 bclk t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz
st16c2552 28 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 f igure 12. c lock t iming f igure 13. m odem i nput /o utput t iming f or c hannels a & b osc clk clk external clock iow # rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active
st16c2552 29 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo f igure 14. d ata b us r ead t iming f igure 15. d ata b us w rite t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# ior# d0-d7 rdtm t cs t rd 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# iow# d0-d7 t cs t wr
st16c2552 30 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 f igure 16. r eceive r eady and i nterrupt t iming [n on -fifo m ode ] for c hannels a & b f igure 17. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled
st16c2552 31 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo f igure 18. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b f igure 19. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
st16c2552 32 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 f igure 20. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b f igure 21. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo no longer empty data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled *int is cleared when the isr is read or when there is at least one character in the fifo. tx txrdy# iow# int* txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo no longer empty tx fifo empty tx fifo empty t t s t si isr is read ier[1] enabled *int is cleared when the isr is read or when there is at least one character in the fifo. at least 1 empty location in fifo t srt tx fifo full t wt
st16c2552 33 rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo package dimensions (44 pin plcc) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a1 0.090 0.120 2.29 3.05 a2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1
34 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet october 2006. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. st16c2552 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 revision history d ate r evision d escription february 2002 4.0 changed to standard style format. text descriptions were clarified and simpli - fied (eg. dma operation, fifo mode vs. non-fifo mode operations etc). clarified timing diagrams. renamed rc lk (receive clock) to bclk (baud clock) and timing symbols. added t ah , t cs and osc. march 2002 4.1 minor clarifications in text descriptions. changed a0-a7 in figures 14 and 15 to a0-a2. september 2003 4.2 changed to single column format. corrected a2 and a0 pin numbers in pin descriptions. added device status to ordering information. devices with top markings of "a2 yyww" and newer have 5v tolerant inputs. devices with top mark - ings of "cc yyww" and older do not have 5v tolerant inputs. october 2006 4.2.1 corrected ordering information. added third digit to revision number.
st16c2552 i rev. 4.2.1 2.97v to 5.5v dual uart with 16-byte fifo table of contents general description........ ................. ................ ................ ............... .............. ........... 1 a pplications ............................................................................................................................... .............. 1 f eatures ............................................................................................................................... ................... 1 f igure 1. st16c2552 b lock d iagram ............................................................................................................................... .................. 1 f igure 2. p in o ut a ssignment ............................................................................................................................... .............................. 2 ordering information ............................................................................................................................. 2 pin descriptions ............ ................ ................ ................. ................ ................. ........... 3 1.0 product description ....................................................................................................... .... 6 2.0 functional descriptions ............................................................................................... 7 2.1 cpu i nterface .............................................................................................................................. ... 7 f igure 3. st16c2552 d ata b us i nterconnections ......................................................................................................................... 7 2.2 d evice r eset .............................................................................................................................. ...... 7 2.3 c hannel a and b s election ............................................................................................................ 7 t able 1: c hannel a and b s elect ............................................................................................................................... ........................ 7 2.4 c hannel a and b i nternal r egisters ............................................................................................ 8 2.5 s imultaneous w rite to c hannel a and b ...................................................................................... 8 2.6 dma m ode .............................................................................................................................. .......... 8 t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode .................................................................................................... 8 2.7 inta and intb o uputs .................................................................................................................... 9 t able 3: inta and intb p ins o peration for t ransmitter ................................................................................................................ 9 t able 4: inta and intb p in o peration f or r eceiver ....................................................................................................................... 9 2.8 c rystal o scillator or e xt . c lock i nput ...................................................................................... 9 f igure 4. t ypical oscillator connections ............................................................................................................................... ......... 9 2.9 p rogrammable b aud r ate g enerator ......................................................................................... 10 f igure 5. e xternal c lock c onnection for e xtended d ata r ate ................................................................................................. 10 f igure 6. o perating f requency c hart . r equires a 2k ohms pull - up resistor on xtal2 pin to increase operating speed .10 t able 5: t ypical data rates with a 14.7456 mh z crystal or external clock .............................................................................. 11 2.10 t ransmitter .............................................................................................................................. ... 11 2.10.1 transmit holding register (thr) - write only ............................................................................ ........... 11 2.10.2 transmitter operation in non-fifo mode .......... .............. .............. ........... ............ ........... .......... ............ 11 f igure 7. t ransmitter o peration in non -fifo m ode ...................................................................................................................... 12 2.10.3 transmitter operation in fifo mode .............. ........................................................................ ............... 12 f igure 8. t ransmitter o peration in fifo m ode ............................................................................................................................. 12 2.11 r eceiver .............................................................................................................................. ......... 12 2.11.1 receive holding register (rhr) - read-only ...... ........................................................................ ......... 13 f igure 9. r eceiver o peration in non -fifo m ode ........................................................................................................................... 13 f igure 10. r eceiver o peration in fifo m ode ............................................................................................................................... .. 13 2.12 i nternal l oopback ..................................................................................................................... 14 f igure 11. i nternal l oop b ack in c hannel a and b........................................................................................................................ 14 3.0 uart internal register s ................................................ ............................................. 15 t able 6: uart channel a and b uart internal registers ............................................................................. ................ 15 t able 7: internal registers description........................................................................................... ................................ 16 4.0 internal register descriptions ........................................................................................ 16 4.1 r eceive h olding r egister (rhr) - r ead - o nly ........................................................................... 16 4.2 t ransmit h olding r egister (thr) - w rite -o nly ......................................................................... 16 4.3 b aud r ate g enerator d ivisors (dll and dlm) - r ead /w rite ................................................... 17 4.4 i nterrupt e nable r egister (ier) - r ead /w rite .......................................................................... 17 4.4.1 ier versus receive fifo inte rrupt mode operation ...... .............. .............. .............. ............... .......... ...... 17 4.4.2 ier versus receive/transmit fi fo polled mode operation................................................................... . 17 4.5 i nterrupt s tatus r egister (isr) - r ead -o nly ............................................................................ 18 4.5.1 interrupt generation: .................................................................................................... ............................ 18 4.5.2 interrupt clearing: ...................................................................................................... .............................. 18 t able 8: i nterrupt s ource and p riority l evel ............................................................................................................................... 18 4.6 fifo c ontrol r egister (fcr) - w rite -o nly ............................................................................... 19 t able 9: t ransmit and r eceive fifo t rigger l evel s election ..................................................................................................... 19 4.7 l ine c ontrol r egister (lcr) - r ead /w rite ................................................................................ 20
st16c2552 ii 2.97v to 5.5v dual uart with 16-byte fifo rev. 4.2.1 t able 10: p arity selection ............................................................................................................................... ................................. 21 4.8 m odem c ontrol r egister (mcr) or g eneral p urpose o utputs c ontrol - r ead /w rite ........ 21 4.9 l ine s tatus r egister (lsr) - r ead o nly ..................................................................................... 22 4.10 m odem s tatus r egister (msr) - r ead o nly ............................................................................. 23 4.11 s cratch p ad r egister (spr) - r ead /w rite ............................................................................... 24 4.12 b aud r ate g enerator r egisters (dll and dlm) - r ead /w rite ............................................... 24 4.13 a lternate f unction r egister (afr) - r ead /w rite ................................................................... 24 t able 11: uart reset conditions for channel a and b ................................................................................. .................. 25 absolute maximum ratings........... ................ ................ ............... .............. ...........26 electrical characteristics ........ ................ ................ ............... .............. ...........26 dc e lectrical c haracteristics ...........................................................................................................26 ac e lectrical c haracteristics ............................................................................................................27 ta=0o to 70oc (-40o to +85oc for industrial grade package ), vcc is 2.97 to 5.5v........ .............. .............. ........ 27 70 pf load where applicable .................................................................................................... .......................... 27 f igure 12. c lock t iming ............................................................................................................................... ..................................... 28 f igure 13. m odem i nput /o utput t iming f or c hannels a & b......................................................................................................... 28 f igure 14. d ata b us r ead t iming ............................................................................................................................... ...................... 29 f igure 15. d ata b us w rite t iming ............................................................................................................................... ..................... 29 f igure 17. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ............................................................... 30 f igure 16. r eceive r eady and i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ............................................................. 30 f igure 18. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b ............................................... 31 f igure 19. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b ................................................ 31 f igure 20. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b ................................... 32 f igure 21. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b.................................... 32 package dimensions (44 pin plcc ) ................. .............. ............... .............. ...........33 table of contents ............................................................................................................. .................... i

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